In bit-parallel CMOS data path architectures, power losses occur due to dynamic hazards, which losses contribute significantly to the total power loss. The power loss of digital static CMOS circuits is essentially determined by the charges to be recharged of the transistor capacitances and of the transmission capacitances. The following holds approximately for the power loss P.sub.t : EQU P.sub.t .congruent..sigma.C.sub.L V.sup.2.sub.DD f.sub.c
C.sub.L thereby designates the transistor capacitance and transmission capacitance to be recharged, V.sub.DD designates the supply voltage, f.sub.c designates the clock frequency and a designates the switching probability.
Static hazards are defined as logical errors in digital circuits that arise due to the different runtimes of the gates used. A simple example of this is shown in FIG. 1. A circuit of CMOS circuit blocks is shown here, consisting essentially of AND gates UG1, UG2, UG3 and bistable flip-flops FF1, FF2. The signals Y.sub.1, Y'.sub.1, Y.sub.1 , Y.sub.1 ', X inside the circuit block of FIG. 1 are shown in FIG. 2, insofar as they are variable. Assume that the signals Y.sub.1 and Y.sub.1 change simultaneously to logical "1" or to logical "0." The corresponding signals Y1' and Y' then appear at the output of the AND-gates UG1 and UG2. If it is assumed that the AND-gate UG2 switches with delay T and the AND-gate UG1 switches without delay, a temporary logical "1" appears as the signal X at the output of the AND-gate UG3, which "1" causes an undesired setting of the subsequent bistable flip-flop FF2. If the switching speeds of the two AND-gates UG1 and UG2 are equal, no hazard occurs. In the last line of FIG. 2, the hazard X is shown at the output of the AND-gate UG3, which occurs due to the delay T of the AND-gate UG2.
Switching processes in which, due to different runtimes, the output of a gate switches several times before reaching its final logical state are designated dynamic hazards.
Up to now, various methods have been used to reduce the switching processes in digital circuits (E. J. Mc Cluskey, Logic Design Principles, Prentice Hall, Englewood Cliffs, N.J. 07632, 1986, T. K. Liu, Synthesis Algorithm for 2-Levels MOS Networks, IEEE Trans. On Computers, Vol. C-24, No. 1, January 1975). One possibility is to minimize the number of logical gates required for a realization of a function. As a rule, the dynamic hazards are thereby also indirectly reduced. In addition, specific programs have been developed for the minimization of the switching frequency and thereby for the reduction of the power loss (J. M. Rabaey, Low Power Digital Design, Proc. ISCA '94, London, Lecture Notes, Chapter 8, May 1994, P. Landman und J. rabaey, Power Estimation for High level Synthesis, Proc. 1993 EDAC Conference, Paris, February 1993). One strategy for the minimization of the dynamic hazards is to try to make all signal paths the same length, if possible. This method is shown in FIG. 3. Circuits of three circuit blocks FA, FB, FC are shown here. While dynamic hazards can occur in the left circuit at the outputs 2 and 3, dynamic hazards no longer occur in the right circuit, provided that the signal runtimes of the blocks FA' and FB' are equal. Digital filters are described in W. Ulbrich und T. G. Noll, Design of Dedicated MOS Digital Filters for High-Speed Applications. Proc., ISCAS' 1985, Kyoto, pp. 255-258, June 1985.